What every computer scientist should know about floating-point arithmetic
ACM Computing Surveys (CSUR)
Division Algorithms and Implementations
IEEE Transactions on Computers
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
Division and Square Root: Digit-Recurrence Algorithms and Implementations
Division and Square Root: Digit-Recurrence Algorithms and Implementations
More on Squaring and Multiplying Large Integers
IEEE Transactions on Computers
Dual-mode floating-point multiplier architectures with parallel operations
Journal of Systems Architecture: the EUROMICRO Journal
A Tool for Unbiased Comparison between Logarithmic and Floating-point Arithmetic
Journal of VLSI Signal Processing Systems
Parameterized floating-point logarithm and exponential functions for FPGAs
Microprocessors & Microsystems
Higher radix and redundancy factor for floating point SRT division
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Multipliers for floating-point double precision and beyond on FPGAs
ACM SIGARCH Computer Architecture News
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This paper presents integer multiplication and division operators dedicated to Virtex-II FPGAs from Xilinx. Those operators are based on small 18脳18 multiplier blocks available in the Virtex-II device family. Various trade-offs are explored (computation decomposition, radix, digit sets . . . ) using specific VHDL generators. The obtained op-eratorslead to speed improvements up to 18% for multiplication and 40% for division compared to standard solutions only based on CLBs.