High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree
IEEE Transactions on Computers
IEEE Transactions on Computers
'Overturned-Stairs' Adder Trees and Multiplier Design
IEEE Transactions on Computers - Special issue on computer arithmetic
Fast multiplication: algorithms and implementation
Fast multiplication: algorithms and implementation
Design issues in high performance floating point arithmetic units
Design issues in high performance floating point arithmetic units
A Reduced-Area Scheme for Carry-Select Adders
IEEE Transactions on Computers
A New Design Technique for Column Compression Multipliers
IEEE Transactions on Computers
167 MHz Radix-4 Floating Point Multiplier
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
Design Strategies for Optimal Multiplier Circuits
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
Reducing the number of counters needed for integer multiplication
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
The SNAP Project: Design of Floating Point Arithmetic Units
ARITH '97 Proceedings of the 13th Symposium on Computer Arithmetic (ARITH '97)
On fast IEEE rounding
How to Half the Latency of IEEE Compliant Floating-Point Multiplication
EUROMICRO '98 Proceedings of the 24th Conference on EUROMICRO - Volume 1
Delay-Optimized Implementation of IEEE Floating-Point Addition
IEEE Transactions on Computers
Systematic IEEE rounding method for high-speed floating-point multipliers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dual-mode floating-point multiplier architectures with parallel operations
Journal of Systems Architecture: the EUROMICRO Journal
A novel IEEE rounding algorithm for high-speed floating-point multipliers
Integration, the VLSI Journal
Fast, Efficient Floating-Point Adders and Multipliers for FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Variable-latency floating-point multipliers for low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Prenormalization rounding in IEEE floating-point operations using a flagged prefix adder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bridge floating-point fused multiply-add design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-Efficient Multiple-Precision Floating-Point Multiplier for Embedded Applications
Journal of Signal Processing Systems
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A new IEEE compliant floating-point rounding algorithm for computing the rounded product from a carry-save representation of the product is presented. The new rounding algorithm is compared with the rounding algorithms of Yu and Zyner [26] and of Quach et al. [17]. For each rounding algorithm, a logical description and a block diagram is given, the correctness is proven, and the latency is analyzed. We conclude that the new rounding algorithm is the fastest rounding algorithm, provided that an injection (which depends only on the rounding mode and the sign) can be added in during the reduction of the partial products into a carry-save encoded digit string. In double precision format, the latency of the new rounding algorithm is $12$ logic levels compared to $14$ logic levels in the algorithm of Quach et al. and $16$ logic levels in the algorithm of Yu and Zyner.