On the Design of IEEE Compliant Floating Point Units
IEEE Transactions on Computers
A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication
IEEE Transactions on Computers - Special issue on computer arithmetic
Delay-Optimized Implementation of IEEE Floating-Point Addition
IEEE Transactions on Computers
Systematic IEEE rounding method for high-speed floating-point multipliers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel IEEE rounding algorithm for high-speed floating-point multipliers
Integration, the VLSI Journal
Variable-latency floating-point multipliers for low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Prenormalization rounding in IEEE floating-point operations using a flagged prefix adder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bridge floating-point fused multiply-add design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-Efficient Multiple-Precision Floating-Point Multiplier for Embedded Applications
Journal of Signal Processing Systems
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A systematic general rounding procedure is proposed. This procedure consists of 2 steps: constructing a rounding table and selecting a prediction scheme. Optimization guidelines are given in each step to minimize the hardware used. This procedure-based rounding method has the additional advantage that verification and generalization are trivial. Two rounding hardware models are described. The first is shown to be identical to that reported by Santoro, et al. The second is more powerful, providing solutions where the first fails. Applying this approach to the IEEE rounding modes for high-speed conventional binary multipliers reveals that round to infinity is more difficult to implement than the round to nearest mode; more adders are potentially needed. Round to zero requires the least amount of hardware. A generalization of this procedure to redundant binary multipliers reveals two major advantages over conventional binary multipliers. First, the computation of the sticky bit consumes considerably less hardware. Second, implementing round to positive and minus infinity modes does not require the examination of the sticky bit, removing a possible worst-case path. A generalization of this approach to addition produces a similar solution to that reported by Quach and Flynn. Although generalizable to other kinds of rounding as well as other arithmetic operations, we only treat the case of IEEE rounding for addition and multiplication; IEEE rounding because it is the current standard on rounding, addition and multiplication because they are the most frequently used arithmetic operations in a typical scientific computation.