Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
An IEEE Compliant Floating-Point Adder that Conforms with the Pipelined Packet-Forwarding Paradigm
IEEE Transactions on Computers
A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication
IEEE Transactions on Computers - Special issue on computer arithmetic
A dual precision IEEE floating-point multiplier
Integration, the VLSI Journal
A Reduced-Area Scheme for Carry-Select Adders
IEEE Transactions on Computers
The SNAP Project: Design of Floating Point Arithmetic Units
ARITH '97 Proceedings of the 13th Symposium on Computer Arithmetic (ARITH '97)
Reduced Latency IEEE Floating-Point Standard Adder Architectures
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
How Many Logic Levels Does Floating-Point Addition Require?
ICCD '98 Proceedings of the International Conference on Computer Design
Using the Reverse-Carry Approach for Double Datapath Floating-Point Addition
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
Leading Zero Anticipation and Detection A Comparison of Methods
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
1-GHz HAL SPARC64® Dual Floating Point Unit with RAS Features
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
On the Design of Fast IEEE Floating-Point Adders
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
On fast IEEE rounding
On the design of high performance digital arithmetic units
On the design of high performance digital arithmetic units
Integration, the VLSI Journal
A design of high speed double precision floating point adder using macro modules
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units
IEEE Transactions on Computers
Digital Circuit Optimization via Geometric Programming
Operations Research
Dual-mode floating-point adder architectures
Journal of Systems Architecture: the EUROMICRO Journal
Low-power leading-zero counting and anticipation logic for high-speed floating point units
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parallel error detection for leading zero anticipation
Journal of Computer Science and Technology
Design issues and implementations for floating-point divide-add fused
IEEE Transactions on Circuits and Systems II: Express Briefs
A survey of hardware designs for decimal arithmetic
IBM Journal of Research and Development
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Abstract--We present an IEEE floating-point adder (FP-adder) design. The adder accepts normalized numbers, supports all four IEEE rounding modes, and outputs the correctly normalized rounded sum/difference in the format required by the IEEE Standard. The FP-adder design achieves a low latency by combining various optimization techniques such as: A nonstandard separation into two paths, a simple rounding algorithm, unification of rounding cases for addition and subtraction, sign-magnitude computation of a difference based on one's complement subtraction, compound adders, and fast circuits for approximate counting of leading zeros from borrow-save representation. We present technology-independent analysis and optimization of our implementation based on the Logical Effort hardware model and we determine optimal gate sizes and optimal buffer insertion. We estimate the delay of our optimized design at 30.6 FO4 delays for double precision operands (15.3 FO4 delays per stage between latches). We overview other IEEE FP addition algorithms from the literature and compare these algorithms with our algorithm. We conclude that our algorithm has shorter latency (-13 percent) and cycle time (-22 percent) compared to the next fastest algorithm.