A dual precision IEEE floating-point multiplier

Delay-Optimized Implementation of IEEE Floating-Point Addition

IEEE Transactions on Computers

Partial product reduction by using look-up tables for M×N multiplier

Integration, the VLSI Journal

Dual-mode floating-point adder architectures

Journal of Systems Architecture: the EUROMICRO Journal

Flexible multi-mode embedded floating-point unit for field programmable gate arrays

Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays