Design issues in high performance floating point arithmetic units
Design issues in high performance floating point arithmetic units
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ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
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ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
On the design of high performance digital arithmetic units
On the design of high performance digital arithmetic units
Instruction set enhancements for reliable computations
Instruction set enhancements for reliable computations
Delay-Optimized Implementation of IEEE Floating-Point Addition
IEEE Transactions on Computers
Dual-Mode Quadruple Precision Floating-Point Adder
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
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Journal of Systems Architecture: the EUROMICRO Journal
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ACM Transactions on Architecture and Code Optimization (TACO)
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Most modern microprocessors provide multiple identical functional units to increase performance. This paper presents dual-mode floating-point adder architectures that support one higher precision addition and two parallel lower precision additions. A double precision floating-point adder implemented with the improved single-path algorithm is modified to design a dual-mode double precision floating-point adder that supports both one double precision addition and two parallel single precision additions. A similar technique is used to design a dual-mode quadruple precision floating-point adder that implements the two-path algorithm. The dual-mode quadruple precision floating-point adder supports one quadruple precision and two parallel double precision additions. To estimate area and worst-case delay, double, quadruple, dual-mode double, and dual-mode quadruple precision floating-point adders are implemented in VHDL using the improved single-path and the two-path floating-point addition algorithms. The correctness of all the designs is tested and verified through extensive simulation. Synthesis results show that dual-mode double and dual-mode quadruple precision adders designed with the improved single-path algorithm require roughly 26% more area and 10% more delay than double and quadruple precision adders designed with the same algorithm. Synthesis results obtained for adders designed with the two-path algorithm show that dual-mode double and dual-mode quadruple precision adders requires 33% and 35% more area and 13% and 18% more delay than double and quadruple precision adders, respectively.