Dual-mode floating-point adder architectures
Journal of Systems Architecture: the EUROMICRO Journal
Flexible multi-mode embedded floating-point unit for field programmable gate arrays
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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Many scientific applications require more accurate computations than double precision or doubleextended precision floating-point arithmetic. This paper presents a dual-mode quadruple precision floating-point adder that also supports two parallel double precision additions. A technique and modifications used to design the dual-mode quadruple precision adder are also applied to implement a dualmode double precision adder, which supports one double precision and two parallel single precision operations. To estimate area and worst case delay, the conventional and the dual-mode double and quadruple precision adders are implemented in VHDL and synthesized. The correctness of all the designs is also tested and verified through extensive simulation. Synthesis results show that the dual-mode quadruple precision adder requires roughly 14% more area than the conventional quadruple precision adder and a worst case delay is 9% longer.