A unified vector/scalar floating-point architecture
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
An IEEE Compliant Floating-Point Adder that Conforms with the Pipelined Packet-Forwarding Paradigm
IEEE Transactions on Computers
Delay-Optimized Implementation of IEEE Floating-Point Addition
IEEE Transactions on Computers
Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units
IEEE Transactions on Computers
Dual-mode floating-point adder architectures
Journal of Systems Architecture: the EUROMICRO Journal
Flexible multi-mode embedded floating-point unit for field programmable gate arrays
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Prenormalization rounding in IEEE floating-point operations using a flagged prefix adder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bridge floating-point fused multiply-add design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Self-Alignment Schemes for the Implementation of Addition-Related Floating-Point Operators
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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