Journal of the ACM (JACM)
A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication
IEEE Transactions on Computers - Special issue on computer arithmetic
The Flagged Prefix Adder and its Applications in Integer Arithmetic
Journal of VLSI Signal Processing Systems
A Reduced-Area Scheme for Carry-Select Adders
IEEE Transactions on Computers
167 MHz Radix-4 Floating Point Multiplier
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
The SNAP Project: Towards Sub-Nanosecond Arithmetic
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
Floating Point Division and Square Root Algorithms and Implementation in the AMD-K7 Microprocessor
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
1-GHz HAL SPARC64® Dual Floating Point Unit with RAS Features
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
On the Design of Fast IEEE Floating-Point Adders
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
On fast IEEE rounding
On the design of high performance digital arithmetic units
On the design of high performance digital arithmetic units
A Regular Layout for Parallel Adders
IEEE Transactions on Computers
A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations
IEEE Transactions on Computers
A novel IEEE rounding algorithm for high-speed floating-point multipliers
Integration, the VLSI Journal
A survey of hardware designs for decimal arithmetic
IBM Journal of Research and Development
Speculative carry generation with prefix adder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper demonstrates howIEEE 754 floating-point standard compliant rounding can be merged with carry-propagate addition in floating-point unit (FPU) designs by using a novel adaptation of the prefix adder. The paper considers add/subtract, multiply, and SRT divide operations and demonstrates that in every case a generic rounding architecture based on a prefix adder with a small amount of additional logic is sufficient to cover all the rounding modes. Critical path analysis shows that the proposed architecture is compatible with contemporary pipelined FPU design practice, while using significantly less logic.