The wave pipeline effect on LUT-based FPGA architectures
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
The Flagged Prefix Adder and its Applications in Integer Arithmetic
Journal of VLSI Signal Processing Systems
Prenormalization rounding in IEEE floating-point operations using a flagged prefix adder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
SNAP - the Stanford subnanosecond arithmetic processor - is an interdisciplinary effort to develop theory, tools, and technology for realizing an arithmetic processor with execution rates under 1 ns. Specific improvements in clocking methods, floating-point addition algorithms, floating-point multiplication algorithms, division and higher-level function algorithms, design tools, and packaging technology were studied. These improvements have been demonstrated in the implementation of several VLSI designs.