Design and realization of high-performance wave-pipelined 8 × 8 b multiplier in CMOS technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Some Notes on Power Management on FPGA-Based Systems
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
The SNAP Project: Towards Sub-Nanosecond Arithmetic
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
Environmental Limits on the Performance of CMOS Wave-Pipelined Circuits
Environmental Limits on the Performance of CMOS Wave-Pipelined Circuits
Wave-pipelined intra-chip signaling for on-FPGA communications
Integration, the VLSI Journal
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