The S/390 G5 Floating Point Unit Supporting Hex and Binary Architectures

Authors:
Eric M. Schwarz;Ronald M. Smith;Christopher A. Krygowski
Affiliations:
-;-;-
Venue:
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
Year:
1999

Citing 0
Cited 7

IBM's S/390 G5 Microprocessor Design

IEEE Micro
The IBM eServer z990 floating-point unit

IBM Journal of Research and Development
Dual-mode floating-point multiplier architectures with parallel operations

Journal of Systems Architecture: the EUROMICRO Journal
Dual-mode floating-point adder architectures

Journal of Systems Architecture: the EUROMICRO Journal
The S/390 G5 floating-point unit

IBM Journal of Research and Development
Architecture and software support in IBM S/390 parallel enterprise servers for IEEE floating-point arithmetic

IBM Journal of Research and Development
VLIW coprocessor for IEEE-754 quadruple-precision elementary functions

ACM Transactions on Architecture and Code Optimization (TACO)

Quantified Score

Hi-index	0.00

Visualization

Abstract

Advances in computer hardware often have little impact until they become accessible to programmers using high-level languages. For example, the IEEE floating-point arithmetic standard provides various rounding modes and exceptions, but it is difficult ...