The Flagged Prefix Adder and its Applications in Integer Arithmetic
Journal of VLSI Signal Processing Systems
Delay-Optimized Implementation of IEEE Floating-Point Addition
IEEE Transactions on Computers
Dual-mode floating-point adder architectures
Journal of Systems Architecture: the EUROMICRO Journal
Low-power leading-zero counting and anticipation logic for high-speed floating point units
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parametric architecture for function calculation improvement
ARCS'07 Proceedings of the 20th international conference on Architecture of computing systems
A survey of hardware designs for decimal arithmetic
IBM Journal of Research and Development
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The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the significand addition. The floating-point adder is implemented in 0.5um CMOS, measures 1.8mm^2, has a 3-cycle latency and implements all rounding modes. A modified version of this floating-point adder can perform accumulation in 2-cycles with a small amount of extra hardware for use in a parallel processor node. This is achieved by feeding back the previous un-normalised but correctly rounded result together with the normalisation distance. A 2-cycle latency floating-point adder architecture with potentially the same cycle time that also employs flagged prefix addition is described. It also incorporates a fast prediction scheme for the true subtraction of significands with an exponent difference of 1, with one less adder.