Concrete mathematics: a foundation for computer science
Concrete mathematics: a foundation for computer science
How to read floating point numbers accurately
PLDI '90 Proceedings of the ACM SIGPLAN 1990 conference on Programming language design and implementation
How to print floating-point numbers accurately
PLDI '90 Proceedings of the ACM SIGPLAN 1990 conference on Programming language design and implementation
A floating point multiplier performing IEEE rounding and addition in parallel
Journal of Systems Architecture: the EUROMICRO Journal
A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication
IEEE Transactions on Computers - Special issue on computer arithmetic
Introduction to Arithmetic for Digital Systems Designers
Introduction to Arithmetic for Digital Systems Designers
An improved algorithm for high-speed floating-point addition
An improved algorithm for high-speed floating-point addition
On fast IEEE rounding
A novel IEEE rounding algorithm for high-speed floating-point multipliers
Integration, the VLSI Journal
Variable-latency floating-point multipliers for low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-Efficient Multiple-Precision Floating-Point Multiplier for Embedded Applications
Journal of Signal Processing Systems
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For performance reasons, many high-speed floating-point multipliers today precompute multiple significand values (SVs) in advance. The final normalization and rounding steps are then performed by selecting the appropriate SV. While having speed advantages, this integrated rounding method complicates the development of the rounding logic significantly, hence, requiring a systematic rounding method. The systematic rounding method, presented in this paper, has three steps: 1) constructing a rounding table; 2) developing a prediction scheme; and 3) performing rounding digits selection (RDS). The rounding table lists all possible SVs that need to be precomputed. Prediction reduces the number of these SVs for efficient hardware implementation while RDS reduces the complexity of the rounding logic. Both prediction and RDS depend on the specifics of the hardware implementation. Two hardware implementations are described. The first one is modeled after that reported by Santoro et al. and the second improved one supports all IEEE rounding modes. Besides allowing systematic hardware optimization, this rounding method has the added advantage that verification and generalization are straightforward.