Leading-One Prediction with Concurrent Position Correction
IEEE Transactions on Computers
An IEEE Compliant Floating-Point Adder that Conforms with the Pipelined Packet-Forwarding Paradigm
IEEE Transactions on Computers
Systematic IEEE rounding method for high-speed floating-point multipliers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A design of high speed double precision floating point adder using macro modules
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units
IEEE Transactions on Computers
Bridge floating-point fused multiply-add design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper describes an improved, IEEE conforming floating-point addition algorithm. This algorithm has only one addition step involving the significand in the worst-case path, hence offering a considerable speed advantage over the existing algorithms, which typically require two to three addition steps.