Design of the IBM RISC System/6000 floating-point execution unit
IBM Journal of Research and Development
Leading-zero anticipator (LZA) in the IBM RISC System/6000 floating-point execution unit
IBM Journal of Research and Development
The SNAP Project: Design of Floating Point Arithmetic Units
ARITH '97 Proceedings of the 13th Symposium on Computer Arithmetic (ARITH '97)
UltraSPARC: the next generation superscalar 64-bit SPARC
COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
Leading-One Prediction Scheme for Latency Improvement in Single Datapath Floating--Point Adders
ICCD '98 Proceedings of the International Conference on Computer Design
A Variable Latency Pipelined Floating-Point Adder
A Variable Latency Pipelined Floating-Point Adder
An improved algorithm for high-speed floating-point addition
An improved algorithm for high-speed floating-point addition
Leading One Detection --- Implementation, Generalization, and Application
Leading One Detection --- Implementation, Generalization, and Application
A Low Power Approach to Floating Point Adder Design for DSP Applications
Journal of VLSI Signal Processing Systems
CMOS VLSI Implementation of a Low-Power Logarithmic Converter
IEEE Transactions on Computers
A design of high speed double precision floating point adder using macro modules
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Low-power leading-zero counting and anticipation logic for high-speed floating point units
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parallel error detection for leading zero anticipation
Journal of Computer Science and Technology
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This paper describes the design of a leading-one prediction (LOP) logic for floating-point addition with an exact determination of the shift amount for normalization of the adder result. Leading-one prediction is a technique to calculate the number of leading zeros of the result in parallel with the addition. However, the prediction might be in error by one bit and previous schemes to correct this error result in a delay increase. The design presented here incorporates a concurrent position correction logic, operating in parallel with the LOP, to detect the presence of that error and produce the correct shift amount. We describe the error detection as part of the overall LOP, perform estimates of its delay and complexity, and compare with previous schemes.