A synthesizable datapath-oriented embedded FPGA fabric
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special edition on the 15th international symposium on FPGAs
International Journal of Parallel, Emergent and Distributed Systems
A Network of Time-Division Multiplexed Wiring for FPGAs
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
Flexible multi-mode embedded floating-point unit for field programmable gate arrays
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Floating-point FPGA: architecture and modeling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
3D-nonFAR: three-dimensional non-volatile FPGA architecture using phase change memory
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Enhancing the area efficiency of FPGAs with hard circuits using shadow clusters
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploration of heterogeneous FPGA architectures
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
Making wide-issue VLIW processors viable on FPGAs
ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
Three-dimensional Integrated Circuits: Design, EDA, and Architecture
Foundations and Trends in Electronic Design Automation
| Hi-index | 0.00 |
Embedded elements, such as block multipliers, are increasingly used in advanced field programmable gate array (FPGA) devices to improve efficiency in speed, area and power consumption. A methodology is described for assessing the impact of such embedded elements on efficiency. The methodology involves creating dummy elements, called Virtual Embedded blocks (VEBs), in the FPGA to model the size, position and delay of the embedded elements. The standard design flow offered by FPGA and CAD vendors can be used for mapping, placement, routing and retiming of designs with VEBs. The speed and resource utilisation of the resulting designs can then be inferred using the FPGA vendor's timing analysis tools. We illustrate the application of this methodology to the evaluation of various schemes of involving embedded elements that support floating-point computations.