A synthesizable datapath-oriented embedded FPGA fabric

Authors:
Steve J. E. Wilton;C. H. Ho;Philip H. W. Leong;Wayne Luk;Brad Quinton
Affiliations:
University of British Columbia, Vancouver, B.C., Canada;Imperial College London, London, England;University of British Columbia, Vancouver, B.C., Canada and University of Hong Kong, Hong Kong;Imperial College London, London, England;University of British Columbia, Vancouver, B.C., Canada
Venue:
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Year:
2007

Citing 12
Cited 3

A reconfigurable arithmetic array for multimedia applications

FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications

IEEE Transactions on Computers
Performance-driven mapping for CPLD architectures

FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Handbook of Applied Cryptography

Handbook of Applied Cryptography
An FPGA architecture with enhanced datapath functionality

FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
PipeRench: A Reconfigurable Architecture and Compiler

Computer
Architecture Design of Reconfigurable Pipelined Datapaths

ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
The chimaera reconfigurable functional unit

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits

Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Measuring the gap between FPGAs and ASICs

Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs

FCCM '06 Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Product-term-based synthesizable embedded programmable logic cores

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications

ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special edition on the 15th international symposium on FPGAs
Floating-point FPGA: architecture and modeling

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimizing floating point units in hybrid FPGAs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

We present an architecture for a synthesizable datapath-oriented Field Programmable Gate Array (FPGA) core which can be used to provide post-fabrication flexibility to a System-on-Chip (SoC). Our architecture is optimized for bus-based operations that are common in signal processing and computation intensive applications. It employs a directional routing architecture, which allows it to be synthesized using standard ASIC design tools and flows. We also describe a proof-of-concept layout of our core. It is shown that the proposed architecture is significantly more area efficient than the best previously reported synthesizable programmable logic core.