Single-Precision Multiplier with Reduced Circuit Complexity for Signal Processing Applications
IEEE Transactions on Computers
Parallel reduced area multipliers
Journal of VLSI Signal Processing Systems - Special issue on application-specific array processors
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
High performance low power array multiplier using temporal tiling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Integer Multiplication with Overflow Detection or Saturation
IEEE Transactions on Computers - Special issue on computer arithmetic
DSP Processor Fundamentals: Architectures and Features
DSP Processor Fundamentals: Architectures and Features
Architectures for Digital Signal Processing
Architectures for Digital Signal Processing
Reduced Power Dissipation Through Truncated Multiplication
VOLTA '99 Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design
VLSI Architecture for Datapath Integration of Arithmetic Over GF(2M) on Digital Signal Processors
ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97) -Volume 1 - Volume 1
Combined IEEE Compliant and Truncated Floating Point Multipliers for Reduced Power Dissipation
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Integer Multipliers with Overflow Detection
IEEE Transactions on Computers
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High-speed arithmetic units in modern processors are expected to support multiplication operations with integers, fractions, and floating-point numbers. This paper presents hardware designs that can perform three modes of multiplication: (1) A double-width multiplication that returns a 2n-bit product. (2) A single-width integer multiplication that returns the n least-significant product bits and an overflow signal. (3) A truncated-fractional multiplication that returns the n most-significant product bits. The presented multipliers achieve up to 50% reduced power dissipation in integer and truncated-fractional multiplication modes of operation. For 16-bit or greater operand sizes the enhanced-functionality multiplier (EFM) designs use less than 10% more hardware compared to the conventional multipliers.