Combined IEEE Compliant and Truncated Floating Point Multipliers for Reduced Power Dissipation

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Venue:
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Year:
2001

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Abstract

Abstract: Truncated multiplication can be used to significantly reduce power dissipation for applications that do not require correctly rounded results. This paper presents a power efficient method for designing floating point multipliers that can perform either correctly rounded IEEE compliant multiplication or truncated multiplication, based on an input control signal. Compared to conventional IEEE floating point multipliers, these multipliers require only a small amount of additional area and delay, yet provide a significant reduction in power dissipation for applications that do not require IEEE compliant results.