On-the-fly conversion of redundant into conventional representations
IEEE Transactions on Computers
Computer arithmetic algorithms
Computer arithmetic algorithms
Communication systems engineering
Communication systems engineering
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
Multiuser Detection
Introduction to Arithmetic for Digital Systems Designers
Introduction to Arithmetic for Digital Systems Designers
Redundant and On-Line CORDIC for Unitary Transformations
IEEE Transactions on Computers
Reduced Power Dissipation Through Truncated Multiplication
VOLTA '99 Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design
On-line Arithmetic for Detection in Digital Communication Receivers
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
Analysis of Column Compression Multipliers
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
Design Alternatives for Parallel Saturating Multioperand Adders
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Combined IEEE Compliant and Truncated Floating Point Multipliers for Reduced Power Dissipation
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
IEEE Transactions on Computers
A Two's Complement Parallel Array Multiplication Algorithm
IEEE Transactions on Computers
Integer fast Fourier transform
IEEE Transactions on Signal Processing
IEEE Transactions on Wireless Communications
Blind adaptive multiuser detection
IEEE Transactions on Information Theory
Multi-user detection for DS-CDMA communications
IEEE Communications Magazine
Performance trends for analog to digital converters
IEEE Communications Magazine
A software radio architecture for linear multiuser detection
IEEE Journal on Selected Areas in Communications
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Truncation in digit-precision is a very important and common operation in embedded system design for bounding the required finite precision and for area-time-power savings. In this paper, we present the use of online arithmetic to provide truncated computations with communication systems as one of the applications. In contrast to truncation in conventional arithmetic, online arithmetic can truncate dynamically and produce both area and time benefits due to the digit-serial nature of computations. This is of great advantage in communication systems where the precision requirements can change dynamically with the environment. While truncation in conventional arithmetic can have significant truncation errors, especially when the output precision is less than the input precision, the redundancy and most significant digit first nature of online arithmetic restricts the truncation error to only the least significant digit of the truncated result. As an application that uses significant truncation in precision, a code matched filter detector for wireless systems is designed using truncated online arithmetic. The detector can provide both hard decisions and soft(er) decisions dynamically as well as interface with other conventional arithmetic circuits or act as a DSP coprocessor. Thus, optimized communication receivers with coexisting conventional arithmetic for saturation and online arithmetic for truncation can now be built. The truncated online arithmetic detector was also verified with a VLSI implementation in an AMI 0.5 \mu MOSIS tiny chip process.