Parallel reduced area multipliers
Journal of VLSI Signal Processing Systems - Special issue on application-specific array processors
Efficient realizations of squaring circuit and reciprocal used in adaptive sample rate notch filters
Journal of VLSI Signal Processing Systems - Special issue on VLSI arithmetic and implementations
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Design of a High-Speed Square Generator
IEEE Transactions on Computers
Structure and Interpretation of Computer Programs
Structure and Interpretation of Computer Programs
DSP Processor Fundamentals: Architectures and Features
DSP Processor Fundamentals: Architectures and Features
Parallel Saturating Fractional Arithmetic Units
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Efficient Lossless Coding of Medical Image Volumes Using Reversible Integer Wavelet Transforms
DCC '98 Proceedings of the Conference on Data Compression
Integer Multipliers with Overflow Detection
IEEE Transactions on Computers
A Binary Multiplication Scheme Based on Squaring
IEEE Transactions on Computers
Synthesis and Comparison of Two's Complement Parallel Multipliers
IEEE Transactions on Computers
A microprocessor for signal processing, the RSP
IBM Journal of Research and Development
Implementation of Digital Electronic Arithmetics and its application in image processing
Computers and Electrical Engineering
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Squaring is commonly used in digital signal processing applications. Significant performance increase can be achieved by supporting squaring in hardware. This paper presents overflow detection methods applicable to integer squarers with unsigned and two's complement operands. These methods are unified for a combined squarer design. Presented methods can be applied to any squarer independent of size and architecture. The proposed squarer designs have approximately 50% less area and delay compared to the conventional squarer designs with overflow detection.