Residue number system arithmetic: modern applications in digital signal processing
Residue number system arithmetic: modern applications in digital signal processing
An Approach to Implementing Multiplication with Small Tables
IEEE Transactions on Computers
Computer arithmetic algorithms
Computer arithmetic algorithms
A method for obtaining digital signatures and public-key cryptosystems
Communications of the ACM
Implementing Multiplication with Split Read-Only Memory
IEEE Transactions on Computers
On Design of Efficient Square Generator
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Integer squarers with overflow detection
Computers and Electrical Engineering
| Hi-index | 14.98 |
Given a binary number N, the simplest way for evaluating its square N2 is the use of ROM look-up tables. For example, the squares of 12-bit numbers can be stored in a ROM of (212脳 24) bits, which takes an area of 3.5mm2 and an access time of 9.96ns with 0.8驴m CMOS process. However, the conventional ROM-table approaches are limited only for small bit-size applications due to the unmanageable increase of the ROM table size. In this paper, a novel design of square generator circuit using a folding approach is presented for high-speed performance applications. Results show that, with the same process, the proposed square generator circuit takes 12.27ns to generate the squares of 40-bit numbers with an area of about 2.88 times that of the (212脳 24)-ROM, i.e., 10mm2. There exists a design trade-off between speed and area. A nested structure is also presented to achieve a 103-bit square generator with a delay of 15.82ns. The bit size can be further increased by adding more levels of the nested structure. The results are promising and thus the proposed approach is well suitable for large bit-size and high-speed applications.