FPGA realization of high performance large size computational functions: multipliers and applications

Authors:
Shuli Gao;Dhamin Al-Khalili;Noureddine Chabini
Affiliations:
Department of Electrical and Computer Engineering, Royal Military College of Canada, Kingston, Canada;Department of Electrical and Computer Engineering, Royal Military College of Canada, Kingston, Canada;Department of Electrical and Computer Engineering, Royal Military College of Canada, Kingston, Canada
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2012

Citing 9
Cited 0

Loopless Algorithms for Generating Permutations, Combinations, and Other Combinatorial Configurations

Journal of the ACM (JACM)
Computer Arithmetic Algorithms

Computer Arithmetic Algorithms
Introduction to Algorithms

Introduction to Algorithms
A Less Recursive Variant of Karatsuba-Ofman Algorithm for Multiplying Operands of Size a Power of Two

ARITH '03 Proceedings of the 16th IEEE Symposium on Computer Arithmetic (ARITH-16'03)
High-level synthesis for large bit-width multipliers on FPGAs: a case study

CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Design and implementation of a high-speed matrix multiplier based on word-width decomposition

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Two's Complement Parallel Array Multiplication Algorithm

IEEE Transactions on Computers
Efficient synthesis of compressor trees on FPGAs

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Introduction to Algorithms, Third Edition

Introduction to Algorithms, Third Edition

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, efficient design methodologies and systematic approaches for realizing large size signed multipliers based on the use of small-size embedded blocks in FPGAs are presented. Two algorithms, delay table and dynamic programming addition optimizations, are used to efficiently organize the addition of partial products. To demonstrate the effectiveness of our approaches, two large size operand computations are realized using our optimized large size multipliers. These functions are complex multiplication and matrix multiplication. The implementations target Xilinx' and Altera's FPGAs. When our approaches are compared to those of traditional techniques, the results show improvements of performance and area usage for both applications.