Introduction to VLSI Systems
A Two's Complement Parallel Array Multiplication Algorithm
IEEE Transactions on Computers
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A high-speed Wallace-tree type combinational multiplier chip has been fabricated as a technology demonstration device using 1.5 驴m NMOS processing. Multiply rates well in excess of 40 mHz have been obtained from laboratory devices. Extensive use of cascaded MOS transmission-gate (or steering) logic resulted in worthwhile improvements in power, average gate delay, and device topology.