An energy-efficient FPGA-based packet processing framework

Authors:
Dániel Horváth;Imre Bertalan;István Moldován;Tuan Anh Trinh
Affiliations:
Budapest University of Technology and Economics, Inter-University Cooperative Research Centre for Telecommunications and Informatics, Budapest, Hungary;Budapest University of Technology and Economics, Inter-University Cooperative Research Centre for Telecommunications and Informatics, Budapest, Hungary;Budapest University of Technology and Economics, Inter-University Cooperative Research Centre for Telecommunications and Informatics, Budapest, Hungary;Budapest University of Technology and Economics, Department of Telecommunications and Mediainformatics, Budapest, Hungary
Venue:
EUNICE'10 Proceedings of the 16th EUNICE/IFIP WG 6.6 conference on Networked services and applications: engineering, control and management
Year:
2010

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Abstract

Modern packet processing hardware (e.g. IPv6-supported routers) demands high processing power, while it also should be power-efficient. In this paper we present an architecture for high-speed packet processing with a hierarchical chip-level power management that minimizes the energy consumption of the system. In particular, we present a modeling framework that provides an easy way to create new networking applications on an FPGA based board. The development environment consists of a modeling environment, where the new application is modeled in SystemC. Furthermore, our power management is modeled and tested against different traffic loads through extensive simulation analysis. Our results show that our proposed solution can help to reduce the energy consumption significantly in a wide range of traffic scenarios.