Communications of the ACM
A Tree Based Router Search Engine Architecture with Single Port Memories
Proceedings of the 32nd annual international symposium on Computer Architecture
A novel reconfigurable hardware architecture for IP address lookup
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
Implementation of Multiple-Valued CAM Functions by LUT Cascades
ISMVL '06 Proceedings of the 36th International Symposium on Multiple-Valued Logic
High Performance Switches and Routers
High Performance Switches and Routers
Non-random generator for IPv6 tables
HOTI '04 Proceedings of the High Performance Interconnects, 2004. on Proceedings. 12th Annual IEEE Symposium
On the numbers of variables to represent sparse logic functions
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Scalable High Throughput and Power Efficient IP-Lookup on FPGA
FCCM '09 Proceedings of the 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines
Memory-Based Logic Synthesis
Scalable Tree-Based Architectures for IPv4/v6 Lookup Using Prefix Partitioning
IEEE Transactions on Computers
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This paper shows an area-efficient and high-speed architecture for IPv6 lookup using a parallel index generation unit (IGU). To reduce the size of memory in the IGU, we use a liner transformation and a row-shift decomposition. Also, this paper shows a design method for the parallel IGU. A single memory realization requires O(2n) memory size, where n denotes the length of prefix, while the IGU requires O(nk) memory size, where k denotes the number of prefixes. In IPv6 prefix lookup, since n is at most 64 and k is about 340 K, the IGU drastically reduces the memory size. Since the parallel IGU has a simple architecture compared with existing ones, it performs lookup by using complete pipelines. We loaded more than 340 K IPv6 pseudo prefixes on the Xilinx Virtex 6 FPGA. Its lookup speed is higher than one giga lookups per second (GLPS). As for the normalized area and lookup speed, our implementation outperforms existing FPGA implementations.