IP lookups using multiway and multicolumn search
IEEE/ACM Transactions on Networking (TON)
Introduction to algorithms
Multiway range trees: scalable IP lookup with fast updates
Computer Networks: The International Journal of Computer and Telecommunications Networking
A B-Tree Dynamic Router-Table Design
IEEE Transactions on Computers
A TCAM-based distributed parallel IP lookup scheme and performance analysis
IEEE/ACM Transactions on Networking (TON)
Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
A Comparative Study of Parallel Prefix Adders in FPGA Implementation of EAC
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
High throughput and large capacity pipelined dynamic search tree on FPGA
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Flashtrie: hash-based prefix-compressed trie for IP route lookup beyond 100Gbps
INFOCOM'10 Proceedings of the 29th conference on Information communications
PRET DRAM controller: bank privatization for predictability and temporal isolation
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Longest Prefix Match and updates in Range Tries
ASAP '11 Proceedings of the ASAP 2011 - 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors
Scalable Tree-Based Architectures for IPv4/v6 Lookup Using Prefix Partitioning
IEEE Transactions on Computers
| Hi-index | 0.00 |
Architectures for tree structures on FPGAs as well as ASICs have been proposed over the years. The exponential growth in the memory size with respect to the tree levels restricts the scalability of these architectures due to limited on-chip memory. For large trees, off-chip memory has to be used. We propose a pipeline architecture on FPGA for large balanced tree structures which achieves both scalability and high throughput. In the proposed architecture, each tree level is mapped onto a single or multiple Processing Elements (PEs) using dual-port distributed RAM, dual-port block RAM and off-chip RAM. We parameterize the pipeline architecture and optimize the performance with respect to scalability and throughput. The resulting architecture for the search tree is dual-threaded and deeply pipelined. It can accept two search requests per clock cycle and operates at a high clock rate of 280MHz. Post place-and-route results show that, by using only 17% of the logic resources and 9% of the BRAM available on a state-of-the-art FPGA, our dual-thread pipelined search tree can perform 560 million search operations per second in a tree containing 512K 64-bit keys.