Scalable high-throughput architecture for large balanced tree structures on FPGA (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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In this paper, we describe an IP-Lookup method for network routing. We extend the basic Range Trie data-structure to support Longest Prefix Match (LPM) and incremental updates. Range Tries improve on the existing Range Trees allowing shorter comparisons than the address width. In so doing, Range Tries scale better their lookup latency and memory requirements with the wider upcoming IPv6 addresses. However, as in Range Trees, a Range Trie does not inherently support LPM, while incremental updates have a performance and memory overhead. We describe the additions required to the basic Range Trie structure and its hardware design in order to store and dynamically update prefixes for supporting LPM. The proposed approach is prototyped in a Virtex4 FPGA and synthesized for 90-nm ASICs. Range Trie is evaluated using Internet Routing Tables and traces of updates. Supporting LPM roughly doubles the memory size of the basic Range Trie, which is still half compared to the second best related work. The proposed design performs one lookup per cycle and one prefix update every four cycles.