Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Eliminating cache conflict misses through XOR-based placement functions
ICS '97 Proceedings of the 11th international conference on Supercomputing
Efficient Hardware Hashing Functions for High Performance Computers
IEEE Transactions on Computers
Longest prefix matching using bloom filters
Proceedings of the 2003 conference on Applications, technologies, architectures, and protocols for computer communications
Tree bitmap: hardware/software IP lookups with incremental updates
ACM SIGCOMM Computer Communication Review
EaseCAM: An Energy and Storage Efficient TCAM-Based Router Architecture for IP Lookup
IEEE Transactions on Computers
Eliminating Conflict Misses Using Prime Number-Based Cache Indexing
IEEE Transactions on Computers
IEEE Transactions on Computers
Fast incremental updates for pipelined forwarding engines
IEEE/ACM Transactions on Networking (TON)
Fast hash table lookup using extended bloom filter: an aid to network processing
Proceedings of the 2005 conference on Applications, technologies, architectures, and protocols for computer communications
Load balancing for parallel forwarding
IEEE/ACM Transactions on Networking (TON)
Chisel: A Storage-efficient, Collision-free Hash-based Network Processing Architecture
Proceedings of the 33rd annual international symposium on Computer Architecture
A TCAM-Based Parallel Architecture for High-Speed Packet Forwarding
IEEE Transactions on Computers
IP-address lookup using LC-tries
IEEE Journal on Selected Areas in Communications
Hint-based cache design for reducing miss penalty in HBS packet classification algorithm
Journal of Parallel and Distributed Computing
| Hi-index | 0.01 |
IP lookup is in the critical data path in a high speed router. In this paper, we propose a new on-chip IP cache architecture for a high performance IP lookup. We design the IP cache along two important axes: cache indexing and cache replacement policies. First, we study various hash performance and employ 2-Universal hashing for our IP cache. Second, coupled with our cache indexing scheme, we present a progressive cache replacement policy by considering Internet traffic characteristics. Our experiments with IP traces show that our IP cache reduces the miss ratio by 15% and a small 32KB IP cache can achieve as high as 2Tbps routing throughput.