M-trie: an efficient approach to on-chip logic minimization

Authors:
S. Ahmand;R. Mahapatra
Affiliations:
Dept. of Comput. Sci., Texas A & M Univ., College Station, TX, USA;Dept. of Comput. Sci., Texas A & M Univ., College Station, TX, USA
Venue:
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Year:
2004

Citing 6
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Abstract

Boolean logic minimization is being increasingly applied to new applications which demands very fast and frequent minimization services. These applications typically offer very limited computing and memory resources rendering the traditional logic minimizers ineffective. We present a new approximate logic minimization algorithm based on ternary trie. We compare its performance with Espresso-II and ROCM logic minimizers for routing table compaction and demonstrate that it is 100 to 1000 times faster and can run with a data memory as little as 16KB. It is also found that proposed approach can support up to 25000 incremental updates per seconds positioning itself as an ideal on-chip logic minimization algorithm.