Routing Table Compaction in Ternary CAM
IEEE Micro
Proceedings of the 40th annual Design Automation Conference
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
A codesigned on-chip logic minimizer
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
M-trie: an efficient approach to on-chip logic minimization
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Compact DSOP and Partial DSOP Forms
Theory of Computing Systems
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This paper presents an efficient hardware architecture of an on-chip logic minimization coprocessor. The proposed architecture employs TCAM cells to provide fastest and memory efficient implementation suitable for emerging on-chip minimization applications. The paper presents a detailed design of the on-chip minimizer and shows that it requires very little hardware resources to achieve acceptable quality of minimization. An incremental insertion and bulk deletion is achieved in 0.25 μs and 3.8 ms respectively and a compaction of 100000 entries in 25 ms using just 300 TCAM entries.