On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor

Authors:
J. Cong;J. Peck
Affiliations:
-;-
Venue:
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Year:
1997

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Abstract

We summarize our study on implementing tautology checking, a fundamental logic synthesis algorithm, using an FPGA based reconfigurable application specific coprocessor. The use of the tautology checking algorithm is first discussed followed by the specifics of hardware accelerator implementation and interface to application software. We compare our hardware accelerator for the tautology check algorithm with the software implementation of the tautology check algorithm in Espresso II (R. Rudell and A. Sangiovanni-Vincentelli, 1987). Our experimental results show that our accelerator is capable of achieving a maximum speedup factor of 2.94 and averaging 1.36 on 110 modified industry benchmarks included with the Espresso II package.