The Concept of Term Exclusiveness and Its Effect on the Theory of Boolean Functions
Journal of the ACM (JACM)
The architecture of concurrent programs
The architecture of concurrent programs
PALMINI—fast Boolean minimizer for personal computers
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Reduced offsets for two-level multi-valued logic minimization
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
State assignment for hardwired VLSI control units
ACM Computing Surveys (CSUR)
PLAYGROUND: minimization of PLAs with mixed ground true outputs
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Two-level logic minimization for low power
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SWAMI: a flexible logic implementation system
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
PHIPLA—a new algorithm for logic minimization
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
PLAYER: a PLA design system for VLSI's
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Worst and Best Irredundant Sum-of-Products Expressions
IEEE Transactions on Computers
Two-Level Minimization of Multivalued Functions with Large Offsets
IEEE Transactions on Computers
PRONTO: Quick PLA product reduction
DAC '83 Proceedings of the 20th Design Automation Conference
HOPLA-PLA optimization and synthesis
DAC '83 Proceedings of the 20th Design Automation Conference
A high level synthesis tool for MOS chip design
DAC '84 Proceedings of the 21st Design Automation Conference
DAC '84 Proceedings of the 21st Design Automation Conference
A logic minimizer for VLSI PLA design
DAC '82 Proceedings of the 19th Design Automation Conference
Input Variable Assignment and Output Phase Optimization of PLA's
IEEE Transactions on Computers
An efficient approach to on-chip logic minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Much of the work in implementing a state machine involves tedious calculations that require no creativity. This report describes the development of a digital-circuit synthesis program that helps reduce the tedium. SMS accepts a high-level description of a state machine and returns equations for implementation that assume a sum-of-products next-state and output functions and that also assume JK or D flip-flops for memory.