Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
A State-Machine Synthesizer—SMS
DAC '81 Proceedings of the 18th Design Automation Conference
An application of multiple-valued logic to a design of programmable logic arrays
MVL '78 Proceedings of the eighth international symposium on Multiple-valued logic
Optimization of primitive gate networks using multiple output two-level minimization
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Simplification of non-deterministic multi-valued networks
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Large-scale SOP minimization using decomposition and functional properties
Proceedings of the 40th annual Design Automation Conference
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The approaches to two-level logic minimization can be classified into two groups: those that use tautology for expansion of cubes and those that use the offset. Tautology based schemes are generally slower and often give somewhat inferior results, because of a limited global picture of the way in which the cube can be expanded. If the offset is used, usually the expansion can be done quickly and in a more global way because it is easier to see effective directions of expansion. The problem with this approach is that there are many functions that have a reasonable size onset and don't care set but the offset is unreasonably large. It was recently shown that for the minimization of such Boolean functions, a new approach using reduced offsets, provides the same global picture and can be computed much faster. In this paper we extend reduced offsets to logic functions with multi-valued inputs.