Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Introduction to VLSI Systems
PRONTO: Quick PLA product reduction
DAC '83 Proceedings of the 20th Design Automation Conference
HOPLA-PLA optimization and synthesis
DAC '83 Proceedings of the 20th Design Automation Conference
A State-Machine Synthesizer—SMS
DAC '81 Proceedings of the 18th Design Automation Conference
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PHIPLA, a new algorithm for logic minimization, is presented. The algorithm sets out to find optimal sum-of-products representations for a set of Boolean functions, thus contributing to area minimization of the Programmable Logic Array corresponding to the set of functions.The results of a comparative study of PHIPLA and two other algorithms, SPAM and PRESTOL-II, are presented. From these results it is concluded that PHIPLA generates representations which are competitive with those generated by SPAM and PRESTOL-II, whilst the algorithm is extremely fast for small problems (up to 12 variables).