HOPLA-PLA optimization and synthesis

Authors:
S. Wimer;N. Sharfman
Affiliations:
NationalL Semiconductor Inc., P.O. Box 3007, Hertzeliya B 46104, ISRAEL;NationalL Semiconductor Inc., P.O. Box 3007, Hertzeliya B 46104, ISRAEL
Venue:
DAC '83 Proceedings of the 20th Design Automation Conference
Year:
1983

Citing 5
Cited 2

Introduction to VLSI Systems

Introduction to VLSI Systems
A State-Machine Synthesizer—SMS

DAC '81 Proceedings of the 18th Design Automation Conference
Automatic PLA synthesis from a DDL-P description

DAC '81 Proceedings of the 18th Design Automation Conference
Techniques for programmable logic array folding

DAC '82 Proceedings of the 19th Design Automation Conference
A logic minimizer for VLSI PLA design

DAC '82 Proceedings of the 19th Design Automation Conference

PHIPLA—a new algorithm for logic minimization

DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Cell compilation with constraints

DAC '84 Proceedings of the 21st Design Automation Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

A system that automates Programmable Logic Array optimization and synthesis for VLSI design is described. PLA logic is defined via a high level Hardware Definition Language. After translation to table representation comes the logic optimization phase, carried out according to a user defined optimization criterion. The geometrical optimization phase follows, supplemented by a manual interactive graphic PLA editor. The system outputs symbolic Layout of the PLA which can be translated into polygon-level layout.