Automatic PLA synthesis from a DDL-P description
DAC '81 Proceedings of the 18th Design Automation Conference
A computer-aided-design system for segmented-folded PLA macro-cells
DAC '81 Proceedings of the 18th Design Automation Conference
A depth-first branch-and-bound algorithm for optimal PLA folding
DAC '82 Proceedings of the 19th Design Automation Conference
Optimal bipartite folding of PLA
DAC '82 Proceedings of the 19th Design Automation Conference
Techniques for programmable logic array folding
DAC '82 Proceedings of the 19th Design Automation Conference
Cell compilation with constraints
DAC '84 Proceedings of the 21st Design Automation Conference
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An integrated, fully automatic software capability that combines Boolean logic translation, Boolean minimization, PLA folding, PLA topology generation, and automatic PLA subchip interfacing to the MP2D standard cell automatic placement and routing program in a single, modular software package is described. Written in ANSI standard FORTRAN, APSS permits the designer to input either arbitrarily formed Boolean equations or a truth table, and to receive a complete MP2D-compatible PLA subchip layout with automatically personalized MP2D subchip interfacing data, as output. As with MP2D, this capability is largely independent of technology and circuit implementation, requiring only an appropriate technology file and cell library consistent with the chosen PLA layout style or “Floor Plan.”