Automatic PLA synthesis from a DDL-P description
DAC '81 Proceedings of the 18th Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
An Improved Min-Cut Algonthm for Partitioning VLSI Networks
IEEE Transactions on Computers
| Hi-index | 14.98 |
The authors present an approach that combines logic minimization and folding for a programmable logic array (PLA). An efficient algorithm is proposed for optimal bipartite column folding. In the algorithm, the authors model the PLA personality matrix as a network and the bipartite PLA folding as a partitioning problem of that network. This folding algorithm is able to find optimal solutions for the benchmarks from the literature. The algorithm also substitutes product terms by their alternatives in order to find the one best suited for folding. The authors combine this algorithm and a logic minimization algorithm into a folding system. When comparing the results to those by a conventional approach, about one half of the benchmarks show area gain if product-term-alternatives exist.