On Input Permutation Technique for Multiple-Valued Logic Synthesis

Authors:
Affiliations:
Venue:
ISMVL '95 Proceedings of the 25th International Symposium on Multiple-Valued Logic
Year:
1995

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Abstract

Abstract: An input permutation technique with respect to multiple valued logic synthesis is introduced. First, it is applied to multiple valued sum of products expressions where sum refers to TSUM. Some upper bounds are clarified on the number of implicants in minimal sum of products expressions for one variable and two variable functions with permuted logic values. An experiment was done on randomly generated functions. The result shows that we can have a saving of approximately 15% on the average by permuting input values. Next, we compare the input permutation with output permutation. As a result, input permutation and output permutation yield a similar saving rate of implicants and output permutation has an advantage of hardware cost and minimization times. Moreover, we show that the use of input permutation for multiple valued sum of products expressions with window literals yields similar results when one uses sum of products expressions with set literals.