On the Optimal Design of Multiple-Valued PLAs
IEEE Transactions on Computers
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Learning with Permutably Homogeneous Multiple-Valued Multiple-Threshold Perceptrons
Neural Processing Letters
Multiple-valued logic synthesis and optimization
Logic Synthesis and Verification
An Optimization Technique for the Design of Multiple Valued PLA's
IEEE Transactions on Computers
On Input Permutation Technique for Multiple-Valued Logic Synthesis
ISMVL '95 Proceedings of the 25th International Symposium on Multiple-Valued Logic
ICCOMP'06 Proceedings of the 10th WSEAS international conference on Computers
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Shows a method of designing programmable logic arrays (PLAs) using multiple-valued input, two-valued output functions (MVITVOFs). A MVITVOF is an extension of the two-valued logic function. An expression for a MVITVOF directly represents a multiple-output PLA with decoders. Each product of the expression corresponds to each column of the PLA, so the number of products; in the expression equals the number of columns of the PLA. The array size of the PLA is proportional to the number of products; the PLA can thus be minimized by minimizing the expression.