MACDAS: multi-level AND-OR circuit synthesis using two-variable function generators
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
DAC '80 Proceedings of the 17th Design Automation Conference
Minimization Algorithms for Multiple-Valued Programmable Logic Arrays
IEEE Transactions on Computers
Learning with Permutably Homogeneous Multiple-Valued Multiple-Threshold Perceptrons
Neural Processing Letters
An Optimization Technique for the Design of Multiple Valued PLA's
IEEE Transactions on Computers
Multiple-Valued Logic Design Using Multiple-Valued EXOR
ISMVL '95 Proceedings of the 25th International Symposium on Multiple-Valued Logic
On Input Permutation Technique for Multiple-Valued Logic Synthesis
ISMVL '95 Proceedings of the 25th International Symposium on Multiple-Valued Logic
Algorithms for physical implementation of multiple-valued circuits
SMO'05 Proceedings of the 5th WSEAS international conference on Simulation, modelling and optimization
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A description is given of the design and analysis of three types of multivalued PLAs (programmable logic arrays). Type 1 PLAs realize functions directly in the form of the max of min of literal functions and constants. In Type 2 PLAs, the body of the PLA is binary and the output is encoded as a multiple-valued logic value. Type 3 PLAs are the same as type 2 PLAs except for the use of 2-bit decoders and a permutation network on the input. Using the number of columns required to realize a given function as a measure to compare PLAs, it is shown that type 3 PLAs are superior to type 2, which in turn are superior to type 1.