Heuristic Minimization of MVL Functions: A Direct Cover Approach
IEEE Transactions on Computers
On the Optimal Design of Multiple-Valued PLAs
IEEE Transactions on Computers
On the Size of PLAs Required to Realize Binary and Multiple-Valued Functions
IEEE Transactions on Computers
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
An Optimization Technique for the Design of Multiple Valued PLA's
IEEE Transactions on Computers
Current-Mode CMOS Multiple-Valued Logic Function Realization Using a Direct Cover Algorithm
ISMVL '95 Proceedings of the 25th International Symposium on Multiple-Valued Logic
Advances in Engineering Software
Computers in Biology and Medicine
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The performance of various heuristic algorithms for minimizing realizations of multiple-valued functions by the charge-coupled device (CCD) and CMOS programmable logic arrays (PLAs) of H.G. Kerkhoff and J.T. Butler (1986) and J.G. Samson (1988), respectively, is analyzed. The functions realized by the PLAs are in sum-of products form, where the sum is ordinary addition truncated to the highest logic value and the product represents the MIN operation of functions of the input variables that are the interval literal operations. Three heuristics, proposed by G. Pomper and J.A. Armstrong (1981), P.W. Besslich (1986), and G.W. Dueck and D.M. Miller (1987), are compared over sets of random and random-symmetric functions. An exact minimization method that is a tree search using backtracking is described. A reduction in the search space is achieved by considering constrained implicant sets and by eliminating some implicants altogether. Even with this improvement, the time required for exact minimization is extremely high when compared to all three heuristics. The case involving only prime implicants is considered, and it is shown that such implicants have marginal value compared to constrained implicant sets. The basis of comparison is the average number of product terms.