Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
On the Optimal Design of Multiple-Valued PLAs
IEEE Transactions on Computers
State minimization of finite state machines using implicit techniques
State minimization of finite state machines using implicit techniques
Efficient Minimization of Multiple-valued Decision Diagrams for Incompletely Specified Functions
ISMVL '03 Proceedings of the 33rd International Symposium on Multiple-Valued Logic
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The task of logic synthesis is to convert the logic description of set function into a netlist of gates that implements the functions. This paper describes the possibility of implementing some combinational and sequential circuits with multiple-valued PLAs (MVPLA), by multiple-valued multiplexers (MVLMUX) or multivalued switches. The algorithms are based on multiple-valued decision diagrams (MDD) representation of the functions. The developed methodology offers some elegant algorithms that automatically map a MMD functions representation in to some certain multi-valued physic circuits. Also, these algorithms convert high logical functions representations into a lower one, very useful taking into account technological restrictions.