Introduction to VLSI Systems
Techniques for programmable logic array folding
DAC '82 Proceedings of the 19th Design Automation Conference
Test generation for programmable logic arrays
DAC '82 Proceedings of the 19th Design Automation Conference
A Design for Testability of Undetectable Crosspoint Faults in Programmable Logic Arrays
IEEE Transactions on Computers
A High Density Programmable Logic Array Chip
IEEE Transactions on Computers
Logic Design of Programmable Logic Arrays
IEEE Transactions on Computers
Fault Analysis and Test Generation for Programmable Logic Arrays (PLA's)
IEEE Transactions on Computers
Detection of Faults in Programmable Logic Arrays
IEEE Transactions on Computers
An Easily Testable Design of Programmable Logic Arrays for Multiple Faults
IEEE Transactions on Computers
A heuristic test-pattern generator for programmable logic arrays
IBM Journal of Research and Development
MINI: a heuristic approach for logic minimization
IBM Journal of Research and Development
A Testable PLA Design with Low Overhead and High Fault Coverage
IEEE Transactions on Computers
A New PLA Design for Universal Testability
IEEE Transactions on Computers
On the Design of Pseudoexhaustive Testable PLAs
IEEE Transactions on Computers - Fault-Tolerant Computing
Design of Pseudoexhaustive Testable PLA with Low Overhead
IEEE Transactions on Computers
Fully testable PLA design with minimal extra input
EURO-DAC '90 Proceedings of the conference on European design automation
Testable PLA design with minimal overheads
Integration, the VLSI Journal
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A new technique for designing easily testable PLA's is presented. The salient features of this technique are: 1) low overhead, 2) high fault coverage, 3) simple design, and 4) little or no impact on normal operation of PLA's. This technique consists of the addition of input lines in such a way that, in test mode, any single product line can be activated and its associated circuitry and device can be tested. Using this technique, all multiple stuck-at faults, as well as all multiple extra and multiple missing device faults, are detected.