Lower Overhead Design for Testability of Programmable Logic Arrays
IEEE Transactions on Computers - The MIT Press scientific computation series
A New Approach to the Design of Testable PLA's
IEEE Transactions on Computers
On the testable design and built-in self-test of plas
On the testable design and built-in self-test of plas
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Introduction to VLSI Systems
DAC '78 Proceedings of the 15th Design Automation Conference
Design of Pseudoexhaustive Testable PLA with Low Overhead
IEEE Transactions on Computers
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A method is presented to design pseudoexhaustive testable (PET) PLAs (programmable logic arrays) that are suitable for BIST (built-in self-test) environments. The key idea of the design is to partition inputs and product lines into groups. During testing, a group of inputs and a group of product lines are selected and tested exhaustively. The proposed design leads to small test sizes and relatively small area overhead. Experimental results on 30 PLAs, comparing test set sizes and area overhead of different BIST PLA designs, are reported.