On the testable design and built-in self-test of plas
On the testable design and built-in self-test of plas
PLATYPUS: a PLA test pattern generation tool
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Introduction to VLSI Systems
DAC '78 Proceedings of the 15th Design Automation Conference
An On-Line Algorithm for the Location of Cross Point Faults in Programmable Logic Arrays
IEEE Transactions on Computers
A Design for Testability of Undetectable Crosspoint Faults in Programmable Logic Arrays
IEEE Transactions on Computers
Multiple Fault Detection in Programmable Logic Arrays
IEEE Transactions on Computers
IEEE Transactions on Computers
Diagnosis of Short-Circuit Faults in Combinational Circuits
IEEE Transactions on Computers
Fault Analysis and Test Generation for Programmable Logic Arrays (PLA's)
IEEE Transactions on Computers
Detection of Faults in Programmable Logic Arrays
IEEE Transactions on Computers
Derivation of Minimum Test Sets for Unate Logical Circuits
IEEE Transactions on Computers
A Design of Programmable Logic Arrays with Universal Tests
IEEE Transactions on Computers
A Hardware Approach to Self-Testing of Large Programmable Logic Arrays
IEEE Transactions on Computers
An Easily Testable Design of Programmable Logic Arrays for Multiple Faults
IEEE Transactions on Computers
Complete Test Sets for Logic Functions
IEEE Transactions on Computers
Implementing a Built-In Self-Test PLA Design
IEEE Design & Test
Universal Test Sets for Logic Networks
IEEE Transactions on Computers
A heuristic test-pattern generator for programmable logic arrays
IBM Journal of Research and Development
MINI: a heuristic approach for logic minimization
IBM Journal of Research and Development
A Testable PLA Design with Low Overhead and High Fault Coverage
IEEE Transactions on Computers
A New PLA Design for Universal Testability
IEEE Transactions on Computers
BIST-PLA: a built-in self-test design of large programmable logic arrays
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
On the Design of Pseudoexhaustive Testable PLAs
IEEE Transactions on Computers - Fault-Tolerant Computing
IEEE Transactions on Computers
The Complexity of Generating Minimum Test Sets for PLA's and Monotone Combinational Circuits
IEEE Transactions on Computers
On the Design of High-Yield Reconfigurable PLA's
IEEE Transactions on Computers
Design of Pseudoexhaustive Testable PLA with Low Overhead
IEEE Transactions on Computers
PLA based synthesis and testing of hazard free logic
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
The effectiveness of different test sets for PLAs
EURO-DAC '90 Proceedings of the conference on European design automation
Fully testable PLA design with minimal extra input
EURO-DAC '90 Proceedings of the conference on European design automation
A BIST design of structured arrays with fault-tolerant layout
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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Programmable logic arrays (PLA's) are extensively used to realize area efficient combinational logic circuits. As the size of the PLA's increases, a cost-effective way to test them is to realize testable PLA's. In this paper a new approach to the design of testable PLA's is presented. The proposed method leads to testable PLA's with minimal area penalty and small number of tests that can be obtained as a by-product of the synthesis procedure, or can be directly obtained from the personality of the PLA's, thus simplifying the test derivation step. Results of an experiment involving 56 PLA's, to compare the test set sizes of differenit testable PLA designs (including the design proposed here) as well as the size of tests derived to detect single faults by algorithmic procedures are also reported.