The Complexity of Generating Minimum Test Sets for PLA's and Monotone Combinational Circuits

Authors:
H. B. Hunt;S. S. Ravi; D. J. Rosenkrantz;A. Chakravarty
Affiliations:
-;-;-;-
Venue:
IEEE Transactions on Computers
Year:
1989

Citing 6
Cited 0

A New Approach to the Design of Testable PLA's

IEEE Transactions on Computers
PLATYPUS: a PLA test pattern generation tool

DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness

Computers and Intractability: A Guide to the Theory of NP-Completeness
STAFAN: An alternative to fault simulation

DAC '84 Proceedings of the 21st Design Automation Conference
A testing strategy for PLAs

DAC '78 Proceedings of the 15th Design Automation Conference
Test generation for programmable logic arrays

DAC '82 Proceedings of the 19th Design Automation Conference

Quantified Score

Hi-index	14.98

Visualization

Abstract

The authors show that the problem of obtaining a minimum complete test set is NP-complete for monotone PLAs even when each product term of the PLA contains at most two literals. Using the ideas developed in the proof of this result, they resolve an open question due to B. Krishnamurthy and S.B. Akers (1984). The authors also show that given a complete test set T, the problem of obtaining a minimum test set contained in T is NP-complete even for two-level monotone circuits.