Introduction to VLSI Systems
Multiple Fault Detection in Programmable Logic Arrays
IEEE Transactions on Computers
Fault Analysis and Test Generation for Programmable Logic Arrays (PLA's)
IEEE Transactions on Computers
Fault Detecting Test Sets for Reed-Muller Canonic Networks
IEEE Transactions on Computers
Detection of Faults in Programmable Logic Arrays
IEEE Transactions on Computers
An introduction to array logic
IBM Journal of Research and Development
Lower Overhead Design for Testability of Programmable Logic Arrays
IEEE Transactions on Computers - The MIT Press scientific computation series
An Alternative to Scan Design Methods for Sequential Machines
IEEE Transactions on Computers - The MIT Press scientific computation series
Testing programmable logic arrays by sum of syndromes
IEEE Transactions on Computers
A New Approach to the Design of Testable PLA's
IEEE Transactions on Computers
A BIST design of structured arrays with fault-tolerant layout
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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In this paper, the problem of fault detection for multiple faults in programmable logic arrays (PLA's) is discussed. An easily testable design of PLA's has been proposed which has the following properties: 1) for a PLA with n inputs, m product terms, there exists a test set such that the test patterns do not depend on the function realized by the PLA; 2) the number of tests to detect multiple stuck type and cross point faults is m(2n + 1) + 4n + 4; 3) the number of additional pins for the testable design is 3; 4) the design philosophy is compatible with the built-in-testing approaches.