A New Approach to the Design of Testable PLA's
IEEE Transactions on Computers
On the testable design and built-in self-test of plas
On the testable design and built-in self-test of plas
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
A Design of Programmable Logic Arrays with Universal Tests
IEEE Transactions on Computers
Partitioning algorithm to enhance VLSI testability
ACM-SE 36 Proceedings of the 36th annual Southeast regional conference
Enhancing random-pattern coverage of programmable logic arrays via masking technique
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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A new method for designing a Built-In Self-Test Programmable Logic Array (BIST-PLA) is presented. In the proposed design, the Test Pattern Generator and the Response Evaluator circuits are very simple. The design requires a re-arrangement of the AND (OR) planes on the basis of number of crosspoints in the product (output) lines in the PLA.The BIST-PLA proposed in this paper is capable of detecting all single stuck-at and crosspoint faults and almost all multiple faults, thus offering fault coverage higher than any of the known BIST designs of PLAs. A program has been written which generates a BIST-PLA. The program was used to study 22 large PLAs from the list of 56 PLAs given in [18]. It was found that the silicon area overhead for almost all these PLAs was lower than those using methods reported in literature [ 10 -17]. Furthermore, the delay performance degradation was found to be within acceptable limits. The program was developed in the Unix environment (4.3beta BSD UNIX) and is integratable with the existing design automation tools.